Semiconductor arrangements, such as integrated circuit arrangements, are modeled using device models, such as a simulation program with integrated circuit emphasis (SPICE) model. Such modeling often occurs prior to fabrication to determine expected performance of semiconductor arrangements. When the modeling indicates undesired performance, a design of a semiconductor arrangement is modified prior to fabrication. Tests are performed during fabrication by measuring wafer acceptance test (WAT) parameters, such as resistance, current, etc. WAT parameters comprise measurements taken at different probe points during various stages of fabrication.